1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to fabrication of a thin dual chip package for an image sensor.
2. Description of Related Art
Personal devices that employ image sensors are rapidly proliferating. Personal digital assistants (PDAs) and cell phones now join digital cameras and camcorders in the family of products that frequently include image-sensing capabilities. Because of their small size and a requirement for portability, such products benefit greatly from the existence of miniature electronics. Any opportunity to reduce the size, weight, and power consumption of image sensing electronic components accrues to the utility of these personal devices and, therefore, accrues to the public in general in terms of utility and convenience.
One way of reducing the size of image sensing components is to fabricate more than one chip in a single package. For example, an image sensor chip such as a complementary metal oxide semiconductor (CMOS) image sensor or charge-coupled device (CCD) may be combined in the same package with a flash memory chip or a digital signal processor (DSP) chip. The resulting structure reduces the chip count in the product by one. Further, if two such chips can be stacked, then the area occupied by the structure can be reduced. In any case, fabricating two chips in one package reduces the amount of packaging material required to fabricate the combination which may contribute to a reduction in weight of the product.
FIG. 1 is a cross-sectional diagram of a prior-art stacked dual chip image sensor package 10 that may appear in a device such as a digital camera. This package comprises a leadframe 15 that includes a supporting pad portion 20 and leads 25 that are used to connect components internal to the image sensor package 10 to terminals external to the image sensor package 10. The supporting pad portion 20 of the leadframe 15 supports two chips in this example. A first chip 30 is a peripheral integrated circuit such as flash memory or a DSP chip mounted on the bottom of the island portion 20 of the leadframe 15, and a second chip 35 is an image sensor chip such as a CMOS image sensor or a CCD mounted on the top of the island portion 20 of the leadframe 15. The first chip 30 has a plurality of bonding pads 45 disposed on an active surface of the first chip 30. The bonding pads 45 are connected to certain ones of leads 25 by a first plurality of wire loops 40. Likewise, the second chip 35 has a plurality of bonding pads 55 as well, the bonding pads 55 being connected to other ones of leads 25 by a second plurality of wire loops 50. The image sensor package 10 is enclosed in a plastic package, an outline 60 of which is shown in FIG. 1, and a transparent lid 65 is mounted to the plastic package to facilitate an incidence of light onto the second chip 35.
Certain parts of the structure illustrated in FIG. 1 contribute to a minimum overall thickness of the image sensor package 10, exclusive of the transparent lid 65. These parts include the first chip 30 having thickness tC1, the island portion 20 of the leadframe 15 having thickness t0, and the second chip 35 having thickness tC2. Additionally, the height tL1 of the first plurality of wire loops 40 and the height tL2 of the second plurality of wire loops 50 contribute to the minimum overall thickness of the image sensor package 10. To summarize, the minimum overall thickness of the prior art image sensor package 10 isT=tC1+tC2+tL1+tL2+t0.  Equation 1
FIG. 2 is a simplified cross-sectional diagram of another prior-art image sensor package 110. This package comprises a substrate 120 on which is mounted a first chip 130. A spacer 121 overlies the first chip 130, and a second chip 135 is mounted on the spacer 121. The first chip 130, the second chip 135, and the substrate 120 all have bonding pads, but only a representative bonding pad 155 disposed on the first chip 130 has been assigned a reference designator in FIG. 2 in order to simplify the diagram. A first plurality of wire loops 140 connect bonding pads on the first chip 130 to bonding pads on the substrate 120. Similarly, a second plurality of wire loops 150 connect bonding pads 155 on the second chip 135 to bonding pads on the substrate 120. A plastic enclosure and transparent lid (not shown) may be included as part of the prior art image sensor package 110.
As was the case for the structure of FIG. 1, certain parts of the structure illustrated in FIG. 2 contribute to a minimum overall thickness of the image sensor package 110. These parts include the first chip 130 having thickness tC1, the substrate 120 having thickness t0, and the second chip 135 having thickness tC2. Additionally, the height tL1 of the first plurality of wire loops 140 and the height tL2 of the second plurality of wire loops 150 contribute to the minimum overall thickness of the image sensor package 110. Thus, the minimum overall thickness of the prior art image sensor package 110 is determined by Equation 1.
The thickness of each of the prior art examples just described includes a thickness of a support member. The example illustrated in FIG. 1 has a thickness that includes the thickness t0 of the island 20 of the leadframe 15 to which are mounted first and second chips 30 and 35. The example illustrated in FIG. 2 has a thickness that includes the thickness t0 of the substrate 120 to which is mounted the first chip 130.
As the capabilities of image sensing products continue to expand, while the demand for smaller and more lightweight products expands, a need continues in the prior art for image sensor packages that are relatively thin and lightweight compared to existing packages. A further need exists for packages that can efficiently dissipate heat generated by image sensor chips.